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Title of the thesis: Enabling cryogenic technologies for superconducting quantum devices

Thesis defender: Joel Hätinen
Opponent: Dr. Joel Ullom, NIST Quantum Sensors Division, USA
Custos: Professor Jukka Pekola, Aalto University School of Science

In this thesis, key components for chip-scale cryogenic coolers are developed. Low-temperature environments enable cutting-edge scientific research and high-performance applications, particularly in the field of superconducting quantum devices. To achieve temperatures close to absolute zero, large and expensive cryorefrigerators are typically utilized. However, to build more scalable and cost-effective cryo-enabled systems, new refrigeration methods have to be developed. One promising technology is the chip-scale cooler based on superconducting tunnel junctions.

As with any refrigerator, thermal insulation, cooling power, and the operating temperature range are the key parameters which define the usefulness of the device. In this thesis, a large inter-chip thermal resistance between two flip-chip-bonded microchips is experimentally demonstrated. The result indicates that a flip-chip structure can be utilized for fabricating chip-scale coolers. Additionally, superconducting through-silicon via interconnects are developed to allow signal transmission in multi-chip assemblies.

The key achievement presented in the thesis is the demonstration of electronic cooling from 2.4 K to below 1.6 K using niobium-based superconducting tunnel junctions. The developed device fills the gap between commercial helium-4 pulse tube refrigerators and existing demonstrations of low-temperature on-chip coolers. The aluminum-niobium junctions fabricated at the wafer scale exhibit state-of-the-art junction characteristics, like low subgap leakage and high cooling power. Furthermore, superconducting tunnel junctions based on silicon, also fabricated at the wafer scale, show suitable parameters to be used for scalable on-chip coolers.

The results demonstrated in this thesis enable the modular design of chip-scale cascade coolers. These coolers are envisioned to support the scaling of several superconducting quantum devices from proof-of-principle to multi-component systems beyond experimental lab environments.

Keywords: 3D integration, flip-chip, on-chip cooler, through-silicon via

Contact information: 
joel.hatinen@vtt.fi 
 

Thesis available for public display 7 days prior to the defence at .